1. Field of the Invention
This invention relates to the field of data processing using a branch cache.
2. Description of the Prior Art
It is known to provide computers that use pipelining techniques to divide the execution of each instruction into several phases, normally called pipeline stages. In order to obtain good performance from such systems it is important that there should be a smooth and continuous flow of instructions through the pipeline. Branch instructions within the stream of instructions being executed tend to interrupt this desired smooth flow. In order to execute a branch instruction, the instruction must be identified as a branch instruction, if the branch is conditional, then the processor must decide whether the branch is to be taken, the target address of the branch must be determined and then the next instruction fetched from that target address. The presence of branch instructions within an instruction stream of a pipelined processing system degrades performance since all of the above processing needs to be performed before the next instruction can be Fed into the pipeline.
In order to reduce the above problem, it is known to provide branch caches. A branch cache shortens the execution time of branch instructions by supplying the target address of a branch from a cache rather than decoding the branch instruction. This is typically achieved by providing a branch cache with cache tags that are the addresses of branch instructions and whose cache data is the address of the instruction at the branch target. Each instruction being fed into the pipeline has its instruction address compared with the cache tags within the branch cache and if a cache hit occurs, then a branch instruction is identified and the branch target address is supplied from the branch cache to cause the processor to start loading instructions into the pipeline from the target address without needing to fully decode the branch instruction.
Examples of such branch caches are described in IEEE Transactions on Computers, Vol. 42, No. 4, April 1993, page 396, "Branch Target Buffer Design and Optimization" by Chris H. Perleberg and Alan Jay Smith and IEEE Technical Report No. CSL-TR-92-553, December 1992, "Branch Prediction Using Large Self History" by John D. Johnson.
Whilst the use of such branch caches is successful in decreasing the delays caused by branch instructions within pipeline systems, it introduces a problem of increasing the power consumption of the system. Having to compare the instruction address of each instruction fed into the pipeline with all of the cache tags of the cache memory consumes a disadvantageously large amount of power. It is a constant aim within the field to reduce power consumption both to assist in the production of portable battery powered equipment and to reduce heat dissipation problems.